
IDT7014S/L
High-Speed 4K x 9 Dual-Port Static RAM
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
Industrial and Commercial Temperature Ranges
7014S12
Com'l Only
7014S15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t AW
t AS
t WP
t WR
t DW
Write Cycle Time
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
12
10
0
10
1
8
____
____
____
____
____
____
15
14
0
12
1
10
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
7
____
7
ns
t DH
Data Hold Time
(3)
0
____
0
____
ns
t WZ
t OW
Write Enable to Output in High-Z (1,2)
Output Active from End-of-Write (1,2,3)
____
0
7
____
____
0
7
____
ns
ns
t WDD
Write Pulse to Data Delay
(4)
____
25
____
30
ns
t DDD
Write Data Valid to Read Data Delay
(4)
____
22
____
25
ns
2528 tbl 09a
7014S20
Com'l & Ind
7014S25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
Write Enable to Output in High-Z
t WC
t AW
t AS
t WP
t WR
t DW
t HZ
t DH
t WZ
Write Cycle Time
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time (1,2)
Data Hold Time (3)
(1,2)
20
15
0
15
2
12
____
0
____
____
____
____
____
____
____
9
____
9
25
20
0
20
2
15
____
0
____
____
____
____
____
____
____
11
____
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
t OW
Output Active from End-of-Write
(1,2,3)
0
____
0
____
ns
t WDD
t DDD
Write Pulse to Data Delay (4)
Write Data Valid to Read Data Delay (4)
____
____
40
30
____
____
45
35
ns
ns
NOTES:
2528 tbl 09b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage
and temperature, the actual t DH will always be smaller than the actual t OW .
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”.
7
6.42